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| general description the max1492/max1494 low-power, 3.5- and 4.5-digit, analog-to-digital converters (adcs) with integrated liquid crystal display (lcd) drivers operate from a single 2.7v to 5.25v power supply. they include an internal refer- ence, a high-accuracy on-chip oscillator, and a triplexed lcd driver. an internal charge pump generates the neg- ative supply needed to power the integrated input buffer for single-supply operation. the adc is configurable for either a ?v or ?00mv input range and outputs its con- version results to an lcd and/or to a microcontroller (?). ? communication is facilitated through an spi -/qspi -/microwire -compatible serial inter- face. the max1492 is a 3.5-digit ( 1999 count) device, and the max1494 is a 4.5-digit (?9,999 count) device. the max1492/max1494 do not require external-preci- sion integrating capacitors, autozero capacitors, crystal oscillators, charge pumps, or other circuitry required with dual-slope adcs (commonly used in panel meter circuits). these devices also feature on-chip buffers for the dif- ferential signal and reference inputs, allowing direct interface with high-impedance signal sources. in addi- tion, they use continuous internal-offset calibration and offer >100db simultaneous rejection of 50hz and 60hz line noise. other features include data hold and peak hold, overrange and underrange detection, and a low- battery monitor. the max1494 comes in a 32-pin, 7mm x 7mm tqfp package, and the max1492 comes in 28-pin ssop and 28-pin pdip packages. all devices in this family operate over the 0? to +70? commercial temperature range. applications digital panel meters hand-held meters digital voltmeters digital multimeters features high resolution max1494: 4.5 digits (?9,999 count) max1492: 3.5 digits (?999 count) sigma-delta adc architecture no integrating capacitors required no autozeroing capacitors required >100db of simultaneous 50hz and 60hz rejection operate from a single 2.7v or 5.25v supply selectable input range of ?00mv or ?v selectable voltage reference: internal 2.048v or external internal high-accuracy oscillator needs no external components automatic offset calibration low power maximum 960? operating current maximum 400? shutdown current small 32-pin 7mm x 7mm tqfp package (4.5 digits), 28-pin ssop package (3.5 digits) triplexed lcd driver spi-/qspi-/microwire-compatible serial interface evaluation kit available (order max1494evkit) max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers ________________________________________________________________ maxim integrated products 1 ordering information 19-2959; rev 3; 5/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin- package resolution (digits) max1492 cai 0 c to +70 c 28 ssop 3.5 MAX1492CNI 0 c to +70 c 28 pdip 3.5 max1494 ccj 0 c to +70 c 32 tqfp 4.5 spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. pin configurations appear at end of data sheet.
max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to gnd............................................................-0.3v to +6v dv dd to gnd ...........................................................-0.3v to +6v ain+, ain- to gnd................................v neg to +(av dd + 0.3v) ref+, ref- to gnd...............................v neg to +(av dd + 0.3v) lowbatt to gnd ...................................-0.3v to (av dd + 0.3v) clk, eoc , cs , din, sclk, dout to gnd .....................................................-0.3v to (dv dd + 0.3v) seg_ and bp_ to gnd ............................-0.3v to (dv dd + 0.3v) v neg to gnd ...........................................-2.6v to (av dd + 0.3v) v disp to gnd ...........................................-0.3v to (dv dd + 0.3v) maximum current into any pin ...........................................50ma continuous power dissipation (t a = +70 c) 28-pin ssop (derate 9.5mw/ c above +70 c) ...........762mw 28-pin pdip (derate 14.3mw/ c above +70 c)......1142.9mw 32-pin tqfp (derate 20.7mw/ c above +70 c).....1652.9mw operating temperature range...............................0 c to +70 c junction temperature ......................................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (av dd = dv dd = +2.7v to +5.25v, gnd = 0, v ref+ - v ref- = 2.048v (external reference). internal clock mode, unless otherwise noted. all specifications are at t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units dc accuracy max1494 -19,999 +19,999 noise-free resolution max1492 -1999 +1999 count 2.000v range 1 integral nonlinearity (note 1) inl 200mv range 1 count range change accuracy (v ain+ - v ain- = 0.100v) on 200mv range / (v ain+ - v ain- = 0.100v) on 2.0v range 10:1 ratio rollover error (see the definitions section) v ain+ - v ain- = full scale, v ain- - v ain+ = full scale 1 count output noise 10 v p-p offset error (zero input reading) offset v in = 0 (note 2) -0 0 reading gain error (note 3) -0.5 +0.5 %fsr offset drift (zero-reading drift) v in = 0 (note 4) 0.1 v/ c gain drift 1 ppm/ c input conversion rate external clock frequency 4.915 mhz external-clock duty cycle 40 60 % internal clock 5 conversion rate external clock, f clk = 4.915mhz 5 hz analog inputs (ain+, ain-, bypass to gnd with 0.1? or greater capacitors) range bit = 0, 2v -2.0 +2.0 ain input-voltage range (note 5) range bit = 1, 200mv -0.2 +0.2 v ain absolute input voltage to gnd -2.2 +2.2 v max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = +2.7v to +5.25v, gnd = 0, v ref+ - v ref- = 2.048v (external reference). internal clock mode, unless otherwise noted. all specifications are at t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units internal clock mode, 50hz and 60hz 2% 100 normal-mode 50hz and 60hz rejection (simultaneously) external clock mode, 50hz and 60hz 2%, f clk = 4.915mhz 120 db common-mode 50hz and 60hz rejection (simultaneously) cmr for 50hz and 60hz 2%, r source < 10k ? 150 db common-mode rejection cmr at dc 100 db input leakage current 10 na input capacitance 10 pf dynamic input current (note 6) -20 +20 na low-battery voltage monitor (lowbatt) lowbatt tripthreshold 2.048 v lowbatt leakage current 10 pa hysteresis 20 mv internal reference (intref bit = 1, ref- = gnd, bypass ref+ to gnd with a 4.7? capacitor) ref output voltage v ref av dd = 5v, t a = +25 c 2.007 2.048 2.089 v ref output short-circuit current 1ma ref output temperature coefficient tc vref av dd = 5v 40 ppm/ c load regulation i source = 0 to 300a, i sink = 0 to 30a 6 mv/a line regulation 50 v/v 0.1hz to 10hz 25 noise voltage 10hz to 10khz 400 v p-p external reference (intref bit = 0, bypass ref+ and ref- to gnd with 0.1? or larger capacitors) ref input voltage differential (v ref+ - v ref- ) 2.048 v absolute ref input voltage to gnd -2.2 +2.2 v internal clock mode, 50hz and 60hz 2% 100 normal-mode 50hz and 60hz rejection (simultaneously) external clock mode, 50hz and 60hz 2%, f clk = 4.915mhz 120 db common-mode 50hz and 60hz rejection (simultaneously) cmr for 50hz and 60hz 2%, r source < 10k ? 150 db common-mode rejection cmr at dc 100 db input leakage current 10 na input capacitance 10 pf dynamic input current (note 6) -20 +20 na max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = +2.7v to +5.25v, gnd = 0, v ref+ - v ref- = 2.048v (external reference). internal clock mode, unless otherwise noted. all specifications are at t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units charge pump (c neg = 0.1?) output voltage v neg -2.60 -2.42 -2.30 v digital inputs (sclk, din, cs , clk) input current i in v in = 0 or dv dd -10 +10 a input low voltage v inl 0.3 x dv dd v input high voltage v inh 0.7 x dv dd v input hysteresis v hyst dv dd = 3.0v 200 mv digital outputs (dout, eoc ) output low voltage v ol i sink = 1ma 0.4 v output high voltage v oh i source = 200a 0.8 x dv dd v tri-state leakage current i l d out only -10 +10 a tri-state output capacitance c out d out only 15 pf power supply av dd voltage av dd 2.70 5.25 v dv dd voltage dv dd 2.70 5.25 v power-supply rejection av dd psrr a (note 7) 80 db power-supply rejection dv dd psrr d (note 7) 100 db av dd = 5v 580 660 av dd current (notes 8, 9) i avdd standby 240 380 a dv dd = 5v 260 320 dv dd = 3.3v 130 180 dv dd current (notes 8, 9) i dvdd standby 10 20 a lcd driver max1492 1.92 x dv dd rms segment on voltage max1494 1.92 x (dv dd - v disp ) v max1492 1/3 x dv dd rms segment off voltage max1494 1/3 x (dv dd - v disp ) v display voltage setup resistor r disp max1494 only 157.5 k ? display multiplex rate 107 hz lcd data-update rate 2.5 hz max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers _______________________________________________________________________________________ 5 timing characteristics (notes 10, 11 and figure 13) (av dd = dv dd = 2.7v to +5.25v, gnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk operating frequency f sclk 0 4.2 mhz sclk pulse-width high t ch 100 ns sclk pulse-width low t cl 100 ns din to sclk setup t ds 50 ns din to sclk hold t dh 0ns cs fall to sclk rise setup t css 50 ns sclk rise to cs rise hold t csh 0ns sclk fall to dout valid t do c load = 50pf (figures 18, 19) 120 ns cs rise to dout disable t tr c load = 50pf (figures 18, 19) 120 ns cs fall to dout enable t dv c load = 50pf (figures 18, 19) 120 ns note 1: integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error and offset error. note 2: offset calibrated. see the offset_cal1 and offset_cal2 sections in the on-chip registers section. note 3: offset nulled. note 4: drift error is eliminated by recalibration at the new temperature. note 5: the input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pa ir. note 6: v ain+ or v ain- = -2.2v to +2.2v. v ref+ or v ref- = -2.2v to +2.2v. all input structures are identical. production tested on ain+ and ref+ only. note 7: measured at dc by changing the power-supply voltage from 2.7v to 5.25v and measuring the effect on the conversion error with external reference. psrr at 50hz and 60hz exceeds 120db with filter notches at 50hz and 60hz (figure 2). note 8: clk and sclk are idle. note 9: power-supply currents are measured with all digital inputs at either gnd or dv dd and with the device in internal clock mode. note 10: all input signals are specified with t rise = t fall = 5ns (10% to 90% of dv dd ) and are timed from a voltage level of 50% of dv dd , unless otherwise noted. note 11: see the serial-interface timing diagrams. max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers 6 _______________________________________________________________________________________ typical operating characteristics (av dd = dv dd = 5v, gnd = 0, external reference mode, ref+ = 2.048v, ref- = gnd, range bit = 1, internal clock mode, t a = +25 c, unless otherwise noted.) max1494 ( 200mv input range) inl vs. output code max1492/94 toc01 output code inl (counts) 10,000 0 -10,000 -0.5 0 0.5 1.0 -1.0 -20,000 20,000 max1494 ( 2v input range) inl vs. output code max1492/94 toc02 output code inl (counts) 10,000 0 -10,000 -0.5 0 0.5 1.0 -1.0 -20,000 20,000 noise distribution max1492/94 toc03 noise (lsb) percentage of units (%) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 5 10 15 20 25 0 -0.2 supply current vs. supply voltage max1492/94 toc04 supply voltage (v) supply current ( a) 4.75 4.25 3.75 3.25 100 200 300 400 500 600 700 0 2.75 5.25 analog supply digital supply max1494 offset error vs. supply voltage max1492/94 toc05 supply voltage (v) offset error (lsb) 4.75 4.25 3.75 3.25 -0.11 -0.06 -0.01 0.04 0.09 0.14 0.19 -0.16 2.75 5.25 max1494 offset error vs. temperature max1492/94 toc06 temperature ( c) offset error (lsb) 60 50 10 20 30 40 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 -0.2 070 max1494 gain error vs. supply voltage max1492/94 toc07 supply voltage (v) gain error (% full scale) 4.75 4.25 3.25 3.75 -0.08 -0.04 -0.06 -0.02 0 0.02 0.04 0.06 0.08 -0.10 2.75 5.25 max1494 gain error vs. temperature max1492/94 toc08 temperature ( c) gain error (% full scale) 60 50 30 40 20 10 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 -0.10 070 internal reference voltage vs. temperature max1492/94 toc09 temperature ( c) reference voltage (v) 60 50 40 30 20 10 2.046 2.045 2.047 2.049 2.048 2.051 2.050 2.053 2.052 2.054 2.044 070 max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers _______________________________________________________________________________________ 7 internal reference voltage vs. analog supply voltage max1492/94 toc10 supply voltage (v) reference voltage (v) 4.75 4.25 3.75 3.25 2.045 2.046 2.047 2.048 2.049 2.050 2.044 2.75 5.25 supply current vs. temperature max1492/94 toc11 temperature ( c) supply current ( a) 60 50 40 30 20 10 100 200 300 400 500 600 700 0 070 analog supply digital supply shutdown supply current vs. temperature max1492/94 toc12 temperature ( c) supply current ( a) 60 50 40 30 20 10 50 100 150 200 250 300 0 070 analog supply digital supply shutdown supply current vs. supply voltage max1492/94 toc13 supply voltage (v) supply current ( a) 4.75 4.25 3.75 3.25 50 100 150 200 250 300 0 2.75 5.25 analog supply digital supply charge-pump output voltage vs. analog supply voltage max1492/94 toc14 supply voltage (v) v neg voltage (v) 4.75 4.25 3.75 3.25 -2.48 -2.46 -2.44 -2.42 -2.40 -2.50 2.75 5.25 v neg startup scope shot max1492/94 toc15 20ms/div 2v/div 1v/div v dd v neg offset error vs. common-mode voltage max1492/94 toc16 common-mode voltage (v) offset error (lsb) 1.5 1.0 -1.5 -1.0 -0.5 0 0.5 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -0.20 -2.0 2.0 data output rate vs. temperature max1492/94 toc17 temperature ( c) data output rate (hz) 60 35 -15 10 4.92 4.98 4.96 4.94 5.00 5.02 5.04 5.06 5.08 5.10 4.90 -40 85 data output rate vs. supply voltage max1492/94 toc18 supply voltage (v) data output rate (hz) 4.74 4.23 3.21 3.72 4.995 4.990 4.985 5.000 5.005 5.010 5.015 5.020 4.980 2.70 5.25 typical operating characteristics (continued) (av dd = dv dd = 5v, gnd = 0, external reference mode, ref+ = 2.048v, ref- = gnd, range bit = 1, internal clock mode, t a = +25 c, unless otherwise noted.) max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers 8 _______________________________________________________________________________________ pin description pin max1492 max1494 name function 1 30 clk external clock input. when the extclk bit in the control register is set, clk is the master clock input for the modulator and the filter (frequency = 4.9152mhz). when the extclk bit in the control register is reset, the internal clock is used. connect clk to gnd or dv dd when the internal oscillator is used. 231dv dd digital power input. connect dv dd to a 2.7v to 5.25v power supply. bypass dv dd to gnd with 0.1f and 4.7f capacitors. 3 32 gnd ground 41av dd analog power input. connect av dd to a 2.7v to 5.25v power supply. bypass av dd to gnd with 0.1f and 4.7f capacitors. 5 2 ain+ positive analog input. positive side of fully differential analog input. bypass ain+ to gnd with a 0.1f or greater capacitor. 6 3 ain- negative analog input. negative side of fully differential analog input. bypass ain- to gnd with a 0.1f or greater capacitor. 7 4 ref- negative reference input. during internal reference operation, connect ref- to gnd. for external reference operation, bypass ref- to gnd with a 0.1f capacitor and set v ref- from -2.2v to +2.2v, provided v ref+ > v ref- . 8 5 ref+ positive reference input. during internal reference operation, connect a 4.7f capacitor from ref+ to gnd. for external reference operation, bypass ref+ to gnd with a 0.1f capacitor and set v ref+ from -2.2v to +2.2v, provided v ref+ > v ref- . 96 lowbatt low-battery input. when v lowbatt < 2.048v (typ), the lowbatt symbol on lcd turns on and the lowbatt bit latches high in the status register. 10 7 eoc active-low, end-of-conversion logic output. a logic-low at eoc indicates that a new adc result is available in the adc result register. 11 8 cs active-low chip-select input. forcing cs low activates the serial interface. 12 9 din serial data input. data present at din is shifted into the internal registers in response to a rising edge at sclk when cs is low. 13 10 sclk serial clock input. apply an external clock to sclk to facilitate communication through the serial bus. sclk can idle high or low. 14 11 dout serial data output. dout presents serial data in response to register queries. data shifts out on the falling edge of sclk. dout goes high impedance when cs is high. 15 12 seg1 lcd segment 1 driver 16 13 seg2 lcd segment 2 driver 17 14 seg3 lcd segment 3 driver 18 15 seg4 lcd segment 4 driver 19 16 seg5 lcd segment 5 driver 20 17 seg6 lcd segment 6 driver 21 18 seg7 lcd segment 7 driver 22 19 seg8 lcd segment 8 driver 23 20 seg9 lcd segment 9 driver max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers _______________________________________________________________________________________ 9 pin description (continued) pin max1492 max1494 name function 24 21 seg10 lcd segment 10 driver 25 25 bp3 lcd backplane 3 driver 26 26 bp2 lcd backplane 2 driver 27 27 bp1 lcd backplane 1 driver 28 29 v neg -2.42v charge-pump output. bypass v neg to gnd with a 0.1f capacitor. 22 seg11 lcd segment 11 driver 23 seg12 lcd segment 12 driver 24 seg13 lcd segment 13 driver 28 v disp temperature-compensation voltage input for lcd. if not using temperature compensation, connect v disp to gnd. see the v disp lcd compensation section. max1494 binary-to-bcd converters and lcd drivers adc input buffers -2.5v ain+ ain- ref+ ref- +2.5v av dd dv dd v disp 2.048v bandgap reference oscillator/ clock sclk din dout eoc seg1 seg13 bp1 bp2 bp3 clk cs serial i/o and control +2.5v gnd a = 1.22 to control charge pump -2.5v lowbatt v neg figure 1. max1494 functional diagram max1492/max1494 detailed description the max1492/max1494 low-power, highly integrated adcs with lcd drivers convert a 2v differential input voltage (one count is equal to 100v for the max1494 and 1mv for the max1492) with a sigma-delta adc and output the result to an lcd or c. an additional 200mv input range (one count is equal to 10v for the max1494 and 100v for the max1492) is available to measure small signals with increased resolution. the devices operate from a single 2.7v to 5.25v power supply and offer 3.5-digit (max1492) or 4.5-digit (max1494) conversion results. an internal 2.048v refer- ence, an internal charge pump, and a high-accuracy on-chip oscillator eliminate external components. the max1492 and max1494 interface with a c using an spi/qspi/microwire-compatible serial interface. data can either be sent directly to the display or to the c first for processing before being displayed. the devices also feature on-chip buffers for the differen- tial input signal and external reference inputs, allowing direct interface with high-impedance signal sources. in addition, they use continuous internal-offset calibration and offer >100db of 50hz and 60hz line noise rejec- tion. other features include data hold and peak hold, overrange and underrange detection, and a low-battery monitor. analog input protection internal protection diodes limit the analog input range from v neg to (av dd + 0.3v). if the analog input exceeds this range, limit the input current to 10ma. internal analog input/reference buffers the max1492/max1494 analog input/reference buffers allow the use of high-impedance signal sources. the input buffer s common-mode input range allows the ana- log inputs and the reference to range from -2.2v to +2.2v. modulator the max1492/max1494 perform analog-to-digital con- versions using a single-bit, 3rd-order, sigma-delta mod- ulator. the sigma-delta modulator converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal information. the modulator quantizes the input signal at a much higher sample rate than the bandwidth of the input. the max1492/max1494 modulator provides 3rd-order frequency shaping of the quantization noise resulting from the single-bit quantizer. the modulator is fully dif- ferential for maximum signal-to-noise ratio and mini- mum susceptibility to power-supply noise. a single-bit data stream is then presented to the digital filter to remove the frequency-shaped quantization noise. digital filtering the max1492/max1494 contain an on-chip digital low- pass filter that processes the data stream from the modulator using a sinc 4 ((sinx/x) 4 ) response. the sinc 4 filter has a settling time of four output data peri- ods (4 x 200ms). the max1492/max1494 have 25% overrange capability built into the modulator and digital filter. the digital filter is optimized for f clk equal to 4.9152mhz. lower clock frequencies can be used; however, 50hz/60hz noise rejection decreases. the frequency response of the sinc 4 filter is measured as follows: where n is the oversampling ratio, and fm = n ? output data rate = 5hz. filter characteristics figure 2 shows the filter frequency response. the sinc 4 characteristic -3db cutoff frequency is 0.228 times the first-notch frequency (5hz). the output data rate for the digital filter corresponds with the positioning of the first notch of the filter s fre- quency response. the notches of the sinc 4 filter are repeated at multiples of the first-notch frequency. the sinc 4 filter provides an attenuation of better than 100db at these notches. for example, 50hz is equal to hz n z z hf n n f fm f fm n () () () () sin sin = ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 11 1 1 1 4 4 3.5- and 4.5-digit, single-chip adcs with lcd drivers 10 ___________________________________________________________________________________________________ frequency (hz) gain (db) 50 40 30 20 10 -160 -120 -80 -40 0 -200 060 figure 2. frequency response of the sinc 4 filter (notch at 60hz) ten times the first-notch frequency and 60hz is equal to 12 times the first-notch frequency. for large step changes at the input, allow a settling time of 800ms before valid data is read. clock modes configure the max1492/max1494 to use either the internal oscillator or an externally applied clock to drive the modulator and filter. set the extclk bit in the con- trol register to 0 to put the device in internal clock mode. set the extclk bit high to put the device in external clock mode. connect clk to gnd or dv dd when using the internal oscillator. the max1492/max1494 ideally operate with a 4.9152mhz clock to achieve maximum rejection of 50hz/60hz common-mode, power-supply, and normal-mode noise. internal clock mode the max1492/max1494 contain an internal oscillator. the power-up condition for the max1492/max1494 is internal clock operation with the extclk bit in the con- trol register equal to 0. using the internal oscillator saves board space by removing the need for an exter- nal clock source. external clock mode for external clock operation, set the extclk bit in the control register high and drive clk with a 4.9152mhz clock source. using an external clock allows for custom conversion rates. a 2.4576mhz clock signal reduces the conversion rate and the lcd update rate by a fac- tor of two. the max1492/max1494 operate with an external clock source of up to 5.05mhz. charge pump the max1492/max1494 contain an internal charge pump to provide the negative supply voltage for the inter- nal analog input/reference buffers. the bipolar input range of the analog input/reference buffers allows this device to accept negative inputs with high source imped- ances. connect a 0.1f capacitor from v neg to gnd. lcd driver the max1492/max1494 contain the necessary back- plane and segment-driver outputs to drive 3.5-digit (max1492) and 4.5-digit (max1494) lcds. the lcd update rate is 2.5hz. figures 4 7 show the connection schemes for a standard lcd. the max1492/max1494 automatically display the results of the adc, if desired. the max1492/max1494 also allow independent control of the lcd driver through the serial interface, allowing for data processing of the adc result before showing the result on the lcd. additionally, each lcd segment can be individually controlled (see the lcd segment- display register sections). triplexing an internal resistor string comprised of three equal- value resistors (52k ? , 1% matching) is used to gener- ate the display drive voltages. on the max1492, one end of the string is connected to dv dd and the other end is connected to gnd. on the max1494, the other end of the resistor string is connected to v disp . note that v lcd should be three times the threshold voltage for the liquid crystal material used (figure 9). the connection diagrams for a typical 7-segment dis- play-font decimal point and annunciators are illustrated in figures 3 and 8. the max1494/max1492 numeric display drivers (4.5 digits, 3.5 digits) use this configura- tion to drive a triplexed lcd with three backplanes and 13 segment-driver lines (10 for 3.5 digits). figures 4 max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers ______________________________________________________________________________________ 11 a xyz g d e f c b dp annunciator a g d e f c b dp annunciator bp1 bp2 bp3 figure 3. connection diagrams for typical 7-segment displays manufacturer website part number description 04-0924-00 3.5 digit, 5v 04-0924-01 3.5 digit, 3v 04-0925-00 4.5 digit, 5v dci, inc. www.dciincorporated.com 04-0925-01 4.5 digit, 3v the following site has links to other custom lcd manufacturers: www.earthlcd.com/mfr.htm table 1. list of custom lcd manufacturers max1492/max1494 and 5 show the assignment of the 4.5-digit display seg- ments, and figures 6 and 7 show the assignment of the 3.5-digit display segments. the voltage waveforms of the backplane lines and y segment line (figure 3) have been chosen as an exam- ple. this line intersects with bp1 to form the a segment, with bp2 to form the g segment, and with bp3 to form the d segment. eight different on/off combinations of the a, g, and d segments and their corresponding waveforms of the y segment line are illustrated in figures 9 and 10. the schematic diagram in figure 8 shows each intersection as a capacitance from seg- ment line to common line. figure 11 illustrates the volt- age across the g segment. the rms voltage across the segment determines the degree of polarization for the liquid crystal material and 3.5- and 4.5-digit, single-chip adcs with lcd drivers 12 ______________________________________________________________________________________ hold low batt peak bp1 bp2 bp3 figure 4. backplane connection for the max1494 (4.5 digits) hold low batt peak seg13: peak, hold, n.c. seg2: a1, g1, d1 seg12: f4, e4, dp4 seg11: a4, g4, d4 seg10: b4, c4, bc5 seg9: f3, e3, dp3 seg8: a3, g3, d3 seg1: b1, c1, n.c. seg3: f1, e1, dp1 seg4: b2, c2, lowbatt seg5: a2, g2, d2 seg6: f2, e2, dp2 seg7: b3, c3, minus annunciator figure 5. segment connection for the max1494 (4.5 digits) thus the contrast of the segment. the rms off voltage is always v lcd / 3, whereas the rms on voltage is always 1.92v lcd / 3. this is illustrated in figure 11. the ratio of rms on to rms off voltage is fixed at 1.92 for a triplexed lcd. figure 12 illustrates contrast vs. applied rms voltage with a v lcd of 3.1v. the rms on voltage is 2.1v, and the rms off voltage is 1.1v. the off segment has a contrast of less than 5%, while the on segments have greater than 85% contrast. if ghosting is present on the lcd, the rms off voltage is too high. choose an lcd with a higher rms off voltage. alternatively, lower the supply or apply a volt- age on v disp to lower the rms off voltage. figures 9 and 10 show the voltage on the lcd s bp_ inputs and the segment inputs during normal operation. max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers ______________________________________________________________________________________ 13 hold low batt peak seg10: peak, hold, bc4 seg2: a1, g1, d1 seg9: f3, e3, dp3 seg8: a3, g3, d3 seg1: b1, c1, n.c. seg3: f1, e1, dp1 seg4: a2, g2, lowbatt seg5: a2, g2, d2 seg6: f2, e2, dp2 seg7: b3, c3, minus annunciator figure 7. segment connection for the max1492 (3.5 digits) hold low batt peak bp1 bp2 bp3 figure 6. backplane connection for the max1492 (3.5 digits) max1492/max1494 the max1492/max1494 allow for full decimal-point con- trol and feature leading zero suppression. use the dp_en, dpset1, and dpset2 bits in the control register to set the value of the decimal point. tables 2 and 3 show the truth tables of the dp_en, dpset1, and dpset2. the truth tables determine decimal-point usage. the max1492/max1494 overrange and underrange display is shown in table 4. reference the max1492/max1494 reference sets the full-scale range of the adc transfer function. with a nominal 2.048v reference, the adc full-scale range is 2v with the range bit equal to 0. with the range bit set to 1, the full-scale range is 200mv. a decreased reference voltage decreases full-scale range (see the transfer functions section). the max1492/max1494 accept either an external ref- erence or an internal reference. the intref bit selects the reference mode (see the control register (read/write) section). for internal-reference operation, set intref to 1, con- nect ref- to gnd and bypass ref+ to gnd with a 4.7f capacitor. the internal reference provides a nom- inal 2.048v source between ref+ and gnd. the inter- nal-reference temperature coefficient is typically 40ppm/ c. the default power-on state sets the max1492/ max1494 to use the external reference with intref cleared to 0. the external reference inputs, ref+ and ref-, are fully differential. for a valid external-reference input, v ref+ must be greater than v ref- . bypass ref+ and ref- with a 0.1f or greater capacitor to gnd in external-reference mode. 3.5- and 4.5-digit, single-chip adcs with lcd drivers 14 ______________________________________________________________________________________ bp1 bp2 bp3 dp dp f e d g ab c xyz figure 8. schematic of display digit dp_en dpset1 dpset2 display output zero input reading 0 0 0 1 8 8 8 8 0 0 0 1 1 8 8 8 8 0 0 1 0 1 8 8 8 8 0 0 1 1 1 8 8 8 8 0 1 0 0 1 8 8 8.8 0.0 1 0 1 1 8 8.8 8 0.00 1 1 0 1 8.8 8 8 0.000 1 1 1 1.8 8 8 8 0.0000 table 2. decimal-point control table (max1494) dp_en dpset1 dpset2 display output zero input reading x 0 0 1 8 8.8 0.0 x 0 1 1 8.8 8 0.00 x 1 0 1.8 8 8 0.000 x 1 1 1 8 8 8 000 table 3. decimal-point control table (max1492) x = don t care. condition max1492 max1494 overrange 1 1 underrange -1 -1 table 4. lcd during overrange and underrange conditions figure 21 shows the max1492/max1494 operating with an external single-ended reference. in this mode, ref- is connected to gnd and ref+ is driven with an exter- nal 2.048v reference. bypass ref+ to gnd with a 0.47f capacitor. figure 20 shows the max1492/max1494 operating with an external differential reference. in this mode, ref- is connected to the top of the strain gauge and ref+ is connected to the midpoint of the resistor-divider of the supply. max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers ______________________________________________________________________________________ 15 1 2 3 1' 2' 3' v+ v h v l v- v+ v h v l v- v+ v h v l v- v+ v h v l v- v+ v h v l v- v+ v h v l v- v+ v h v l v- v lcd bp1 bp2 bp3 all off a on g, d off g on a, d off d on a, g off frequency = 107hz 1, 2, 3 - - bp high with respect to segment (bp+ time) 1', 2', 3' - - bp low with respect to segment (bp- time) bp1 active during 1 and 1' bp2 active during 2 and 2' bp3 active during 3 and 3' v+ = dv dd , v h = 2/3 dv dd v l = 1/3 v lcd , v- = gnd or v disp v lcd = d vdd - v disp (max1494) v lcd = d vdd - gnd (max1492) figure 9. lcd voltage waveform combinations 1 4 (bp_, seg2/5/8) max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers 16 ______________________________________________________________________________________ 1 2 3 1' 2' 3' v+ v h v l v- v+ v h v l v- v+ v h v l v- v+ v h v l v- v+ v h v l v- v+ v h v l v- v+ v h v l v- v lcd bp1 bp2 bp3 all off a, d on g off a, g on d off g, d on a off frequency = 107hz 1, 2, 3 - - bp high with respect to segment (bp+ time) 1', 2', 3' - - bp low with respect to segment (bp- time) bp1 active during 1 and 1' bp2 active during 2 and 2' bp3 active during 3 and 3' v+ = dv dd , v h = 2/3 dv dd v l = 1/3 v lcd , v- = gnd or v disp v lcd = d vdd - v disp (max1494) v lcd = d vdd - gnd (max1492) figure 10. lcd voltage waveform combinations 5 8 (bp_, seg2/5/8) max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers ______________________________________________________________________________________ 17 1 2 3 1' 2' 3' v lcd -v p 0 v rms = v lcd / 3 off v p -v p 0 v rms = v lcd / 3 off v p -v p 0 v rms = 1.92v lcd / 3 on v p -v p 0 v rms = 1.92v lcd / 3 on all off 1, 2, 3 - - bp high with respect to segment (bp+ time) 1', 2', 3' - - bp low with respect to segment (bp- time) bp1 active during 1 and 1' bp2 active during 2 and 2' bp3 active during 3 and 3' v g = v y - v bp2 (difference between segment line y and bp2 voltage) voltage contrast ratio = v rms on / v rmsoff = 1.922v a on g, d off a, g on d off all on figure 11. voltage waveforms on the g segment max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers 18 ______________________________________________________________________________________ 012345 applied voltage (v rms ) 0 10 20 30 40 50 60 70 80 90 100 contrast (%) t a = +25 c v on = 2.1v rms = -10 c = 0 c = +10 c = -30 c v off = 1.1v rms + - figure 12. contrast vs. applied rms voltage max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers ______________________________________________________________________________________ 19 cs sclk din dout t csh t cl t ds t dh t dv t ch t do t tr t csh t css figure 13. detailed timing diagram sclk cs din dout 1 0 rs4 rs3 rs2 rs1 d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 rs0 x d15 d14 d13 d12 d11 d10 control byte data byte figure 14. serial-interface 16-bit write timing diagram cs sclk din dout 1 0 rs4 rs3 rs2 rs1 d7 d6 d5 d4 d3 d2 d1 d0 rs0 x control byte data byte figure 15. serial-interface 8-bit write timing diagram max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers 20 ______________________________________________________________________________________ sclk cs din dout 1 1 a4 a3 a2 a1 a0 x d7 d6 d5 d4 d3 d2 d1 d0 control byte data byte figure 17. serial-interface 8-bit read timing diagram 6k ? 6k ? dout dout gnd gnd dv dd c load 50pf c load 50pf a) v oh to high-z b) v ol to high-z figure 18. load circuits for disable time 6k ? 6k ? dout dout gnd gnd dv dd c load 50pf c load 50pf b) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol figure 19. load circuits for enable time sclk cs din dout 1 1 rs4 rs3 rs2 rs1 rs0 x d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 d15 d14 d13 d12 d11 d10 control byte data byte figure 16. serial-interface 16-bit read timing diagram max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers ______________________________________________________________________________________ 21 applications information serial interface the spi/qspi/microwire serial interface consists of a chip select ( cs ), a serial clock (sclk), a data in (din), a data out (dout), and an asynchronous eoc output. eoc provides an asynchronous end-of-conversion sig- nal with a period of 200ms (f clk = 4.9152mhz or inter- nal clock mode). the max1492 updates the data register when eoc goes high. data is valid in the adc result registers when eoc returns low. the serial inter- face provides access to 12 on-chip registers, allowing control to all the power modes and functional blocks. table 5 lists the address and read/write accessibility of all the registers. a logic-high on cs tri-states dout and causes the max1492/max1494 to ignore any signals on sclk and din. to clock data into or out of the internal shift regis- ter, drive cs low. sclk synchronizes the data transfer. the rising edge of sclk clocks din into the shift regis- ter, and the falling edge of sclk clocks dout out of the shift register. din and dout are transferred msb- first (data is left justified). figures 13 17 show the detailed serial-interface timing diagrams for the 8- and 16-bit read/write operations. all communication with the max1492/max1494 begins with a command byte on din, where the first logic 1 on din is recognized as the start bit (msb) for the com- mand byte. the following seven clock cycles load the command into a shift register. these 7 bits specify which of the registers are accessed next, and whether a read or write operation takes place. transitions on the serial clock after the command byte transfer cause a write or read from the device until the correct number of bits have been transferred (8 or 16). once this has occurred, the max1492/max1494 wait for the next com- mand byte. cs must not go high between data trans- fers. if cs is toggled before the end of a write or read operation, the device mode may be unknown. clock in 32 zeros to clear the device state and reset the interface so it is ready to receive a new command byte. on-chip registers the max1492/max1494 contain 12 on-chip registers. these registers configure the various functions of the device and allow independent reading of the adc results and writing to the lcd. table 5 lists the address and size of each register. the first of these registers is the status register. the 8-bit status register contains the status flags for the adc. the second register is the 16-bit control register. this register sets the lcd controls, range modes, power-down modes, offset calibration, and the reset-register function (clr). the third register is the 16-bit overrange register, which sets the overrange limit of the analog input. the fourth register is the 16-bit underrange register, which sets the underrange limit of the analog input. registers 5 through 7 contain the display data for the individual seg- ments of the lcd. the eighth register contains the cus- tom offset value. the ninth register contains the 16 msbs of the adc conversion result. the tenth register contains the lcd data. the eleventh register contains the peak analog input value. the last register contains the lower 4 lsbs of the 20-bit adc conversion result. register number address rs [4:0] name width access 1 00000 status register 8 read only 2 00001 control register 16 r/ w 3 00010 overrange register 16 r/ w 4 00011 underrange register 16 r/ w 5 00100 lcd segment-display register 1 16 r/ w 6 00101 lcd segment-display register 2 16 r/ w 7 00110 lcd segment-display register 3 8 r/ w 8 00111 adc custom-offset register 16 r/ w 9 01000 adc result-register 1 (16 msbs) 16 read only 10 01001 lcd data register 16 r/ w 11 01010 peak register 16 read only 12 10100 adc result-register 2 (4 lsbs) 8 read only all other addresses reserved table 5. register address table max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers 22 ______________________________________________________________________________________ start: start bit. the first 1 clocked into the max1492/max1494 is the first bit of the command byte. (r/ w ): read/ write . set this bit to 1 to read from the specified register. set this bit to 0 to write to the selected register. note that certain registers are read-only. write com- mands to a read-only register are ignored. (rs4?s0): register address bits. rs4 to rs0 specify which register is accessed. x: don t care. msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start (1) r/ w rs4 rs3 rs2 rs1 rs0 x this register contains the status of the conversion results. sign: latched negative-polarity indicator. latches high when the result is negative. clears by reading the status register, unless the condition remains true. over: overrange bit. latches high if an over- range condition occurs (the adc result is larger than the value in the overrange reg- ister). clears by reading the status regis- ter, unless the condition remains true. under: underrange bit. latches high if an under- range condition occurs (the adc result is less than the value in the underrange regis- ter). clears by reading the status register, unless the condition remains true. low_batt: low-battery bit. latches high if the voltage at the lowbatt is lower than 2.048v (typ). clears by reading the status register, unless the condition remains true. drdy: data-ready bit. latches high to indicate a completed conversion result with valid data. read the adc result-register 1 to clear this bit. msb lsb sign over under low_batt drdy 0 0 0 this register is the primary control register for the max1492/max1494. it is a 16-bit read/write register. it is used to indicate the desired clock and reference source. it sets the lcd controls, range modes, power- down modes, offset calibration, and the reset register function (clr). msb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 spi/ adc extclk intref dp_en dpset2 dpset1 pd_dig pd_ana lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hold peak range clr seg_sel offset_cal1 offset_cal2 0 status register (read only): control register (read/write): command byte (write only): default values: 0000h default values: 00h max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers ______________________________________________________________________________________ 23 spi/ adc : (default = 0) display select bit. the spi/ adc bit controls selection of the data fed into the lcd data register. a 1 in this location selects spi/qspi/ microwire data (the user writes this data to the lcd data register). a 0 in this location selects the adc result register data, unless hold or peak functions are active (see table 6). extclk: (default = 0) external clock select bit. the extclk bit controls selec- tion of the internal clock or an exter- nal clock source. a 1 in this location selects the signal at the clk input as the clock source. a 0 in this location selects the internal clock oscillator. toggle the pd_dig and pd_ana after changing the extclk bit. intref: (default = 0) reference select bit. for internal reference operation, set intref to 1. for external reference operation, set intref to 0. dp_en: (default = 0) decimal-point enable bit. see tables 2 and 3. dpset[2:1]: (default = 00) decimal-point selection bits. see tables 2 and 3. hold: (default = 0) hold bit. when set to 1, the lcd register does not update from the adc conversion results and holds the last result on the lcd. the max1492/max1494 continue to per- form conversions during hold (see table 6). peak: (default = 0) peak bit. when set to 1 (and the hold bit is set to 0), the lcd shows the result stored in the peak register (see table 6). pd_ana: (default = 0) power-down analog select bit. when set to 1, the analog circuits (analog modulator and adc input buffers) go into the power-down mode. when set to 0, the device is in full power-up mode. pd_dig: (default = 0) power-down digital select bit. when set to 1, the digital circuits (digital filter and lcd drivers) go into power-down mode. this also resets the values of the internal sram (in the digital filter) to zeros. when set to 0, the device returns to full power-up mode. range: (default = 0) input-range select bit. when set to 0, the input voltage range is 2v. when set to 1, the input voltage range is 200mv. toggle the pd_dig and pd_ana after changing the range bit. clr: (default = 0) clear-all-registers bit. when set to 1, all the registers reset to their power-on reset states when cs makes a low-to-high transition. seg_sel: (default = 0) lcd segment-selection bit. when set to 1, the lcd segment drivers use the lcd segment regis- ters to display individual segments that can form letters or numbers or other information on the display. the lcd data register is not displayed. send the data first to the lcd seg- ment-display registers and then set this bit high (see table 6). offset_cal1: (default = 0) automatic-offset enable bit. when set to 1, the max1492/ max1494 disable automatic offset cali- bration. when this bit is set to 0, auto- matic offset calibration is enabled. offset_cal2: (default = 0) enhanced offset- calibration start bit (max1494 only and range = 1). to achieve the low- est possible offset in the 200mv input range, perform an enhanced offset calibration by setting this bit to 1. the calibration takes about 9 cycles (1800ms). after the calibration completes, set this bit to 0 to resume adc conversions. note: when changing any one of the following control bits: offset_cal1 , range, pd_ana, pd_dig, intref, and extclk, wait 800ms before reading the adc results. max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers 24 ______________________________________________________________________________________ default values: 7cf0h (for max1492, +1999) 4e1fh (for max1494, +19,999) the overrange register is a 16-bit read/write register (d15 is the msb). when the conversion result exceeds the value in the overrange register, the over bit in the status register latches to 1. the lcd shows a 1 fol- lowed by 4 dashes for the max1494 or a 1 followed by 3 dashes for the max1492 (see table 4). the data is represented in two s complement format. seg_sel spi/ adc hold peak displays values from 1 x x x lcd segment registers 0 1 x x lcd display register (user written) 0 0 1 x lcd display register 0 0 0 1 peak register 0 0 0 0 adc result register table 6. lcd priority table x = don t care. underrange register (read/write): overrange register (read/write): msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default values: 8300h (for max1492, -2000) b1e0h (for max1494, -20,000) the underrange data register is 16-bit read/write regis- ter (d15 is the msb). when the conversion result falls below the value in the underrange register, the undr bit in the status register sets to 1. the lcd shows a -1 followed by 4 dashes for the max1494 or a -1 followed by 3 dashes for the max1492 (see table 4). the data is represented in two s complement format. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default values: 0000h the lcd segment-display register 1 is a 16-bit read/write register. when the seg-sel bit (in the con- trol register) is set to 1, the max1492/max1494 provide direct access to individual lcd segments. the bits in the lcd segment-display register determine if a seg- ment is on or off. write a 0 to this register to turn on a segment and a 1 to turn off a segment. msb lsb a2 g2 d2 f2 e2 dp2 ann b1 c1 a1 g1 d1 f1 e1 dp1 0 lcd segment-display register 1 (read/write): max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers ______________________________________________________________________________________ 25 default values: 0000h the lcd segment-display register 2 is a 16-bit read/write register. when the seg-sel bit (in the con- trol register) is set to 1, the max1492/max1494 provide direct access to individual lcd segments. the bits in the lcd segment-display register determine if a seg- ment is on or off. write a 0 to this register to turn on a segment and a 1 to turn off a segment. dp1 : segment dp driver bit of digit 1. the default value turns on the lcd segment. e1 : segment e driver bit of digit 1. the default value turns on the lcd segment. f1 : segment f driver bit of digit 1. the default value turns on the lcd segment. d1 : segment d driver bit of digit 1. the default value turns on the lcd segment. g1 : segment g driver bit of digit 1. the default value turns on the lcd segment. a1 : segment a driver bit of digit 1. the default value turns on the lcd segment. c1 : segment c driver bit of digit 1. the default value turns on the lcd segment. b1 : segment b driver bit of digit 1. the default value turns on the lcd segment. ann : custom annunciator. the default value turns on the lcd segment. dp2 : segment dp driver bit of digit 2. the default value turns on the lcd segment. e2 : segment e driver bit of digit 2. the default value turns on the lcd segment. f2 : segment f driver bit of digit 2. the default value turns on the lcd segment. d2 : segment d driver bit of digit 2. the default value turns on the lcd segment. g2 : segment g driver bit of digit 2. the default value turns on the lcd segment. a2 : segment a driver bit of digit 2. the default value turns on the lcd segment. msb lsb f4 e4 dp4 minus b3 c3 a3 g3 d3 f3 e3 dp3 low batt b2 c2 0 c2 : segment c driver bit of digit 2. the default value turns on the lcd segment. b2 : segment b driver bit of digit 2. the default value turns on the lcd segment. lowbatt : lowbatt driver bit. the default value turns on the lowbatt annunciator. dp3 : segment dp driver bit of digit 3. the default value turns on the lcd segment. e3 : segment e driver bit of digit 3. the default value turns on the lcd segment. f3 : segment f driver bit of digit 3. the default value turns on the lcd segment. d3 : segment d driver bit of digit 3. the default value turns on the lcd segment. g3 : segment g driver bit of digit 3. the default value turns on the lcd segment. a3 : segment a driver bit of digit 3. the default value turns on the lcd segment. c3 : segment c driver bit of digit 3. the default value turns on the lcd segment. b3 : segment b driver bit of digit 3. the default value turns on the lcd segment. minus : minus-sign driver bit. the default value turns on the lcd segment. dp4 : segment dp driver bit of digit 4. the default value turns on the lcd segment (max1494 only). e4 : segment e driver bit of digit 4. the default value turns on the lcd segment (max1494 only). f4 : segment f driver bit of digit 4. the default value turns on the lcd segment (max1494 only). lcd segment-display register 2 (read/write): max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers 26 ______________________________________________________________________________________ default values: 00h the lcd segment-display register 3 is an 8-bit read/write register. when the seg-sel bit (in the con- trol register) is set to 1, the max1492/max1494 provide direct access to individual lcd segments. the bits in the lcd segment-display register determine if a seg- ment is on or off. write a 0 to turn on a segment and a 1 to turn off a segment. msb lsb peak hold bc_ b4 c4 a4 g4 d4 d4 : segment d driver bit of digit 4. the default value turns on the lcd segment (max1494 only). g4 : segment g driver bit of digit 4. the default value turns on the lcd segment (max1494 only). a4 : segment a driver bit of digit 4. the default value turns on the lcd segment (max1494 only). c4 : segment c driver bit of digit 4. the default value turns on the lcd segment (max1494 only). b4 : segment b driver bit of digit 4. the default value turns on the lcd segment (max1494 only). bc_ : segment bc_ driver bit. for the max1494, this bit enables bc5. for the max1492, this bit enables bc4. the default value turns on the lcd segment. hold : hold-sign driver bit. the default value turns on the hold annunciator. peak : peak-sign driver bit. the default value turns on the peak annunciator. default values: 0000h in addition to automatic offset calibration, the max1492/max1494 offer a user-defined custom-offset 16-bit read/write register. the final result of the adc conversion is the input after autocalibration minus the value in the custom offset. the custom offset value is stored in this register. d15 is the msb. the data is rep- resented in two s complement format. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default values: 0000h the adc result-register 1 is a 16-bit read-only register. this register stores the 16 msbs of the adc result. the data is represented in two s complement format. for the max1494, the data is 16-bit and d15 is the msb. for the max1492, the data is 12-bit, d15 is the msb, and d4 is the lsb. msb lsb (max1492) lsb (max1494) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lcd segment-display register 3 (read/write): adc custom offset-calibration register (read/write): adc result-register 1 (read only): max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers ______________________________________________________________________________________ 27 default values: 0000h the peak data register is a 16-bit read-only register. set the peak bit to 1 to enable the peak function. this register stores the peak value of the adc conversion result. first, the current adc result is saved to the peak register. then, the new adc conversion result is compared to this value. if the new value is larger than the value in the peak register, the max1492/max1494 save the new value to the peak register. if the new value is less than the value in the peak register, the value in the peak register remains unchanged. set the peak bit to 0 to clear the value in the peak regis- ter. the peak function is only valid for the range of -19,487 to +19,999 for the max1494 and -1217 to +1999 for the max1492. the data is represented in two s complement format. for the max1494, the data is 16-bit and d15 is the msb. for the max1492, the data is 12-bit, d15 is the msb, and d4 is the lsb followed by four trailing sub-bits. default values: 0000h the lcd data register is a 16-bit read/write register. this register updates from the adc result register 1, the peak register, or from the serial interface by selecting spi/ adc bit, peak bit, and hold bit in the control reg- ister (see table 6). the data is represented in two s complement format. for the max1494, the data is 16-bit and d15 is the msb. for the max1492, the data is 12-bit, d15 is the msb, and d4 is the lsb, followed by four trailing sub-bits. msb lsb (max1492) lsb (max1494) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb (max1492) lsb (max1494) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb d3d2d1d00000 default values: 00h the adc result-register 2 is an 8-bit read-only register. this register stores the 4 lsbs of the adc result. use this result with the result in adc result-register 1 to form a 20-bit two s complement conversion result. lcd data register (read/write): peak register (read only): adc result-register 2 (read only): max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers 28 ______________________________________________________________________________________ power-on reset at power-up, the serial interface, lcd driver, digital fil- ter, and modulator circuits reset. the registers return to their default values. allow time for the reference to set- tle before starting calibration. offset calibration the max1492/max1494 offer on-chip offset calibration. the device offset-calibrates during every conversion when the offset_cal1 bit is 0. enhanced offset calibra- tion is only needed in the max1494 when range = 1. it is performed on demand by setting the offset_cal2 bit to 1. power-down modes the max1492/max1494 feature independent power- down control of the analog and digital circuitry. writing a 1 to the pd_dig and pd_ana bits in the control register powers down the analog and digital circuitry, reducing the supply current to 400a. pd_dig powers down the digital filter and lcd drivers, while pd_ana powers down the analog modulator and adc input buffers. v disp lcd compensation (max1494 only) adequate display contrast can be obtained in most applications by connecting v disp to gnd. in applica- tions where a wide temperature range is expected, the voltage levels for some triplexed lcds may need to vary with temperature to maintain good display contrast and viewing angle. the amount of temperature compensa- tion depends upon the type of liquid crystal used. display manufacturers usually specify the temperature variation of the lcd thresholds voltage (rms on - rms off ), which is approximately 1/3 of the peak dis- play voltage. the peak display voltage is equal to dv dd - v disp (max1494 only). therefore, a typical -4mv/ c temperature coefficient of an lcd threshold corre- sponds to a +12mv/ c temperature coefficient at v disp . peak the max1492/max1494 feature peak-detection circuit- ry. when activated (peak bit = 1), the devices display only the highest voltage measured to the lcd. hold the max1492/max1494 feature data-hold circuitry. when activated (hold bit = 1), the devices display the current reading on the lcd. low battery the max1492/max1494 feature a low-battery detection input. when the voltage at lowbatt drops below 2.048v (typ), the lowbatt bit of the status register goes high and the lowbatt segment of the lcd turns on. strain gauge measurement connect the differential inputs of the max1492/ max1494 to the bridge network of the strain gauge. in figure 20, the analog supply voltage powers the bridge network and the max1492/max1494 along with the ref- erence voltage. the max1492/max1494 handle an analog input-voltage range of 200mv and 2v full scale. the analog/reference inputs of the parts allow the analog input range to have an absolute value of anywhere between -2.2v and +2.2v. thermocouple measurement figure 21 shows a connection from a thermocouple to the max1492/max1494. in this application, the max1492/max1494 take advantage of the on-chip input buffers that allow large source impedances on the front end. the decoupling capacitors reduce noise pickup from the thermocouple leads. to place the differential voltage from the thermocouple at a suitable common- mode voltage, the ain- input of the max1492/max1494 is biased to gnd. use an external temperature sensor, such as the ds75, and a c to perform cold junction- temperature compensation. 4?0ma transmitter low-power, single-supply operations make the max1492/max1494 ideal for loop-powered 4 20ma transmitters. loop-powered transmitters draw their power from the 4 20ma loop, limiting the transmitter circuitry to a current budget of 4ma. tolerances in the loop further limit this current budget to 3.5ma. since the max1492/max1494 only consume 950a, a total of 2.55ma remains to power the remaining transmitter cir- cuitry. figure 22 shows a block diagram for a loop- powered 4 20ma transmitter. 4?0ma measurement to measure 4 20ma signals, connect a shunt resistor across ain+ and ain- to create the 2v or 200mv input voltage (figure 23). transfer functions figures 24 27 show the transfer functions of the max1492/max1494. the output data is stored in the adc data register in two s complement. a -1 in the adc result register displays -0 on the lcd as shown in figures 24 27. negative values on the lcd are offset by 1. for example, -100 in the adc result reg- ister appears as -99 on the lcd. supplies, layout, and bypassing when using analog and digital supplies from the same source, isolate the digital supply from the analog sup- ply with a low-value resistor (10 ? ) or ferrite bead. for max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers ______________________________________________________________________________________ 29 best performance, ground the max1492/max1494 to the analog ground plane of the circuit board. avoid running digital lines under the device because they can couple noise onto the device. run the analog ground plane under the max1492/max1494 to mini- mize coupling of digital noise. make the power-supply lines to the max1492/max1494 as wide as possible to provide low-impedance paths and reduce the effects of glitches on the power-supply line. shield fast-switching signals, such as clocks, with digital ground to avoid radiating noise to other sections of the board. avoid running clock signals near the analog inputs. avoid crossover of digital and analog signals. running traces that are on opposite sides of the board at right angles to each other reduces feedthrough effects. good decoupling is important when using high-resolu- tion adcs. decouple the supplies with 0.1f and 4.7f ceramic capacitors to gnd. place these components as close to the device as possible to achieve the best decoupling. see the max1494 evaluation kit manual for the recom- mended layout. the evaluation kit includes a fully assembled and tested evaluation board. definitions inl integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line is either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. inl for the max1492/max1494 is measured using the end- point method. dnl differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. rollover error rollover error is defined as the absolute-value differ- ence between a near positive full-scale reading and near negative full-scale reading. rollover error is tested by applying a near full-scale positive voltage, swapping ain+ and ain-, and then adding the results. zero input reading ideally, with ain+ connected to ain- the max1492/ max1494 lcd is 0 or -0. zero input reading is the mea- sured deviation from the ideal 0 and the actual mea- sured point. gain error gain error is the amount of deviation between the mea- sured full-scale transition point and the ideal full-scale transition point. common-mode rejection common-mode rejection (cmr) is the ability of a device to reject a signal that is common to both input terminals. the common-mode signal can be either an ac or a dc signal or a combination of the two. cmr is often expressed in decibels. normal-mode 50hz and 60hz rejection (simultaneously) normal-mode rejection is a measure of how much out- put changes when a 50hz and 60hz signal is injected into only one of the differential inputs. the max1492/ max1494 sigma-delta converter uses its internal digital filter to provide normal-mode rejection to both 50hz and 60hz power-line frequencies simultaneously. power-supply rejection ratio power-supply rejection ratio (psrr) is the ratio of the input-supply change (in volts) to the change in the con- verter output (in volts). it is typically measured in decibels. max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers 30 ______________________________________________________________________________________ sensor max1492 max1494 isolation barrier gnd gnd 4 spi 4 spi 3 spi p/ c dac v+ v+ r gain r ofst r fdbk c c voltage regulator 1.8.8.8.8 r y r x r sense v in+ v in- 4 20ma loop interface figure 22. 4 20ma transmitter max1492 max1494 max6062 +5v +2.048v temp sensor thermocouple junction 0.1 f 0.47 f spi c ain+ ain- ref+ ref- gnd figure 21. thermocouple application with max1492/max1494 max1492 max1494 av dd dv dd dout din sclk 4.7 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f analog supply ferrite bead r ref r r active gauge dummy gauge ref+ ref- ain+ ain- gnd eoc cs 4.7 f 0.1 f figure 20. strain-gauge application with max1492/max1494 max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers ______________________________________________________________________________________ 31 0.1 f r ain- ain+ 4 20ma r = 100 ? for 2v range 10 ? for 200mv range 0.1 f max1492 max1494 1.8.8.8.8 figure 23. 4 20ma measurement >4e1fh 4e1fh 0002h 0001h 0000h ffffh fffeh fffdh b1e0h max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers ______________________________________________________________________________________ 33 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v neg bp1 bp2 bp3 seg10 seg9 seg1 seg8 seg7 seg6 seg5 seg4 seg3 seg2 dout sclk din cs eoc lowbatt ref+ ref- ain- ain+ av dd gnd dv dd clk pdip/ssop top view max1492 max1494 tqfp 32 28 29 30 31 25 26 27 dv dd clk v neg v disp gnd bp1 bp2 bp3 10 13 15 14 16 11 12 9 din dout sclk seg2 seg1 seg4 seg3 seg5 17 18 19 20 21 22 23 seg12 24 seg13 seg11 seg10 seg9 seg8 seg7 seg6 2 3 4 5 6 7 8 cs eoc lowbatt ref+ ref- ain- ain+ 1 av dd pin configurations chip information transistor count: 79,435 process: bicmos max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers 34 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 32l/48l,tqfp.eps ssop.eps package outline, ssop, 5.3 mm 1 1 21-0056 c rev. document control no. approval proprietary information title: notes: 1. d&e do not include mold flash. 2. mold flash or protrusions not to exceed .15 mm (.006"). 3. controlling dimension: millimeters. 4. meets jedec mo150. 5. leads to be coplanar within 0.10 mm. 7.90 h l 0 0.301 0.025 8 0.311 0.037 0 7.65 0.63 8 0.95 max 5.38 millimeters b c d e e a1 dim a see variations 0.0256 bsc 0.010 0.004 0.205 0.002 0.015 0.008 0.212 0.008 inches min max 0.078 0.65 bsc 0.25 0.09 5.20 0.05 0.38 0.20 0.21 min 1.73 1.99 millimeters 6.07 6.07 10.07 8.07 7.07 inches d d d d d 0.239 0.239 0.397 0.317 0.278 min 0.249 0.249 0.407 0.328 0.289 max min 6.33 6.33 10.33 8.33 7.33 14l 16l 28l 24l 20l max n a d e a1 l c h e n 1 2 b 0.068 max1492/max1494 3.5- and 4.5-digit, single-chip adcs with lcd drivers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 35 ? 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. pdipn.eps package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) |
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